A methodology to reuse random IP stimuli in an SoC functional verification environment - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

V. S. Rashmi, Giridhar Somayaji, Sirisha Bhamidipathi. A methodology to reuse random IP stimuli in an SoC functional verification environment. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-5, IEEE, 2015. [doi]

This author has not been identified. Look up 'V. S. Rashmi' in GoogleThis author has not been identified. Look up 'Giridhar Somayaji' in GoogleThis author has not been identified. Look up 'Sirisha Bhamidipathi' in Google

runs on WebDSL