Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha. Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access, 9:108119-108130, 2021. [doi]

Authors

Sithara Raveendran

This author has not been identified. Look up 'Sithara Raveendran' in Google

Pranose J. Edavoor

This author has not been identified. Look up 'Pranose J. Edavoor' in Google

Nithin Kumar Yernad Balachandra

This author has not been identified. Look up 'Nithin Kumar Yernad Balachandra' in Google

M. H. Vasantha

This author has not been identified. Look up 'M. H. Vasantha' in Google