Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha. Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access, 9:108119-108130, 2021. [doi]
@article{RaveendranEBV21,
title = {Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic},
author = {Sithara Raveendran and Pranose J. Edavoor and Nithin Kumar Yernad Balachandra and M. H. Vasantha},
year = {2021},
doi = {10.1109/ACCESS.2021.3100892},
url = {https://doi.org/10.1109/ACCESS.2021.3100892},
researchr = {https://researchr.org/publication/RaveendranEBV21},
cites = {0},
citedby = {0},
journal = {IEEE Access},
volume = {9},
pages = {108119-108130},
}