An area efficient 10-bit time mode hybrid DAC with current settling error compensation

Nivethithaa Ravikumar, Zaniar Hoseini, Kye-Shin Lee, S. I. Hariharan, Yong-Min Lee. An area efficient 10-bit time mode hybrid DAC with current settling error compensation. In IEEE 58th International Midwest Symposium on Circuits and Systems, MWSCAS 2015, Fort Collins, CO, USA, August 2-5, 2015. pages 1-4, IEEE, 2015. [doi]

Abstract

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