Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology

Ramin Razmdideh, Mohsen Saneei. Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology. I. J. Circuit Theory and Applications, 46(6):1264-1271, 2018. [doi]

Abstract

Abstract is missing.