A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

Reeshen Reddy, Saurabh Sinha. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. Microelectronics Journal, 46(4):310-319, 2015. [doi]

@article{ReddyS15,
  title = {A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance},
  author = {Reeshen Reddy and Saurabh Sinha},
  year = {2015},
  doi = {10.1016/j.mejo.2015.02.001},
  url = {http://dx.doi.org/10.1016/j.mejo.2015.02.001},
  researchr = {https://researchr.org/publication/ReddyS15},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {46},
  number = {4},
  pages = {310-319},
}