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A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet. A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electronic Testing, 32(4):407-421, 2016. [doi]

Authors

Guillaume Renaud

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Manuel J. Barragan

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Asma Laraba

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Haralampos-G. D. Stratigopoulos

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Salvador Mir

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Hervé Le Gall

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Hervé Naudet

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