Guillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet. A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electronic Testing, 32(4):407-421, 2016. [doi]
@article{RenaudBLSMLN16,
title = {A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs},
author = {Guillaume Renaud and Manuel J. Barragan and Asma Laraba and Haralampos-G. D. Stratigopoulos and Salvador Mir and Hervé Le Gall and Hervé Naudet},
year = {2016},
doi = {10.1007/s10836-016-5599-8},
url = {http://dx.doi.org/10.1007/s10836-016-5599-8},
researchr = {https://researchr.org/publication/RenaudBLSMLN16},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {32},
number = {4},
pages = {407-421},
}