Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs - researchr publication authors

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Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragan, Salvador Mir. Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. In 35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017. pages 1-6, IEEE, 2017. [doi]

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