Minimizing the Number of Test Configurations for Different FPGA Families

Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. Minimizing the Number of Test Configurations for Different FPGA Families. In 8th Asian Test Symposium (ATS 99), 16-18 November 1999, Shanghai, China. pages 363-368, IEEE Computer Society, 1999. [doi]

Authors

Michel Renovell

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Jean Michel Portal

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Joan Figueras

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Yervant Zorian

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