Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli. Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectronics Reliability, 54(6-7):1412-1420, 2014. [doi]

Authors

Siavash Rezaei

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Seyed Ghassem Miremadi

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Hossein Asadi

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Mahdi Fazeli

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