Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli. Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. Microelectronics Reliability, 54(6-7):1412-1420, 2014. [doi]
@article{RezaeiMAF14,
title = {Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates},
author = {Siavash Rezaei and Seyed Ghassem Miremadi and Hossein Asadi and Mahdi Fazeli},
year = {2014},
doi = {10.1016/j.microrel.2014.03.003},
url = {http://dx.doi.org/10.1016/j.microrel.2014.03.003},
researchr = {https://researchr.org/publication/RezaeiMAF14},
cites = {0},
citedby = {0},
journal = {Microelectronics Reliability},
volume = {54},
number = {6-7},
pages = {1412-1420},
}