Woogeun Rhee. Design of low-jitter 1-GHz phase-locked loops for digital clock generation. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 520-523, IEEE, 1999. [doi]
@inproceedings{Rhee99,
title = {Design of low-jitter 1-GHz phase-locked loops for digital clock generation},
author = {Woogeun Rhee},
year = {1999},
doi = {10.1109/ISCAS.1999.780796},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1999.780796},
tags = {design},
researchr = {https://researchr.org/publication/Rhee99},
cites = {0},
citedby = {0},
pages = {520-523},
booktitle = {International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA},
publisher = {IEEE},
isbn = {0-7803-5471-0},
}