DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research

Juergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao. DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research. In John Wawrzynek, Katherine Compton, editors, Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. pages 115-118, ACM, 2011. [doi]

@inproceedings{RibutzkaHCG11,
  title = {DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research},
  author = {Juergen Ributzka and Yuhei Hayashi and Fei Chen and Guang R. Gao},
  year = {2011},
  doi = {10.1145/1950413.1950438},
  url = {http://doi.acm.org/10.1145/1950413.1950438},
  tags = {architecture},
  researchr = {https://researchr.org/publication/RibutzkaHCG11},
  cites = {0},
  citedby = {0},
  pages = {115-118},
  booktitle = {Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011},
  editor = {John Wawrzynek and Katherine Compton},
  publisher = {ACM},
  isbn = {978-1-4503-0554-9},
}