A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication

Rodrigue Rizk, Dominick Rizk, Frederic Rizk, Ashok Kumar 0001, Magdy A. Bayoumi. A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication. In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022. pages 1675-1679, IEEE, 2022. [doi]

@inproceedings{RizkRR0B22,
  title = {A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication},
  author = {Rodrigue Rizk and Dominick Rizk and Frederic Rizk and Ashok Kumar 0001 and Magdy A. Bayoumi},
  year = {2022},
  doi = {10.1109/ISCAS48785.2022.9937531},
  url = {https://doi.org/10.1109/ISCAS48785.2022.9937531},
  researchr = {https://researchr.org/publication/RizkRR0B22},
  cites = {0},
  citedby = {0},
  pages = {1675-1679},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022},
  publisher = {IEEE},
  isbn = {978-1-6654-8485-5},
}