Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs

Gabriel Rodriguez-Canal, Nick Brown 0002, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus. Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs. In Nele Mentens, Leonel Sousa, Pedro Trancoso, Nikela Papadopoulou, Ioannis Sourdis, editors, 33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023. pages 10-18, IEEE, 2023. [doi]

Abstract

Abstract is missing.