Table of Contents

• PrefaceIoannis Sourdis, Nele Mentens, Leonel Sousa, Pedro Trancoso. [doi]
• Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level SynthesisRobert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede. 1-9 [doi]
• Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAsGabriel Rodriguez-Canal, Nick Brown 0002, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus. 10-18 [doi]
• An Open-Source Framework for Efficient Numerically-Tailored ComputationsLouis Ledoux, Marc Casas. 19-26 [doi]
• HPTA: A High Performance Transformer Accelerator Based on FPGAYuntao Han, Qiang Liu. 27-33 [doi]
• HyperGRAF: Hyperdimensional Graph-Based Reasoning Acceleration on FPGAHanning Chen, Ali Zakeri, Fei Wen, Hamza Errahmouni Barkam, Mohsen Imani. 34-41 [doi]
• An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented PruningShiqing Li, Shien Zhu, Xiangzhong Luo, Tao Luo, Weichen Liu. 42-48 [doi]
• Token Packing for Transformers with Variable-Length InputsTiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang 0005, Lei He 0001. 49-56 [doi]
• Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture CaptureKimia Talaei Khoozani, Arash Ahmadian Dehkordi, Vaughn Betz. 57-64 [doi]
• SPADES: A Productive Design Flow for Versal Programmable LogicTan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek. 65-71 [doi]
• VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement OptimizationRuichen Chen, Shengyao Lu, Mohamed A. Elgammal, Peter Chun, Vaughn Betz, Di Niu. 72-78 [doi]
• Automated Masking of FPGA-Mapped DesignsNicolai Müller, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori, Amir Moradi 0001. 79-85 [doi]
• fpgaHART: A Toolflow for Throughput-Oriented Acceleration of 3D CNNs for HAR onto FPGAsPetros Toupas, Christos-Savvas Bouganis, Dimitrios Tzovaras. 86-92 [doi]
• Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information ReuseHaishuang Fan, Jingya Wu, Wenyan Lu, Xiaowei Li 0001, Guihai Yan. 93-100 [doi]
• FSSD: FPGA-Based Emulator for SSDsLuyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seungwon Min, Wen-mei W. Hwu, Deming Chen. 101-108 [doi]
• FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001. 109-115 [doi]
• Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable ArchitecturePengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing. 116-122 [doi]
• Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAsShaden M. Alismail, Dirk Koch. 123-129 [doi]
• Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAsAmin Mohaghegh, Vaughn Betz. 130-136 [doi]
• Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder GraphsRémi Garcia 0002, Anastasia Volkova. 137-143 [doi]
• Optimization Techniques for Hestenes-Jacobi SVD on FPGAsLukas Stasytis, Zsolt István. 144-150 [doi]
• Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based ApproachJosé Oliver 0002, Carlos Álvarez 0001, Teresa Cervero, Xavier Martorell, John D. Davis, Eduard Ayguadé. 151-158 [doi]
• MSDF-SGD: Most-Significant Digit-First Stochastic Gradient Descent for Arbitrary-Precision TrainingChangjun Song, Yongming Tang, Jiyuan Liu 0006, Sige Bian, Danni Deng, He Li 0008. 159-165 [doi]
• DiAD - Distributed Acceleration for Datacenter FPGAsJoshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas, William B. Toms, Mikel Luján, John Goodacre. 166-173 [doi]
• FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data LayoutYang Yang 0111, Weihang Long, Rajgopal Kannan, Viktor K. Prasanna. 174-181 [doi]
• FPGA-Accelerated Causal Discovery with Conditional Independence Test PrioritizationCe Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes. 182-188 [doi]
• SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAsTobias Hahn, Stefan Wildermann, Jürgen Teich. 189-196 [doi]
• A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGABaoze Zhao, Wenjin Huang, Yihua Huang 0005. 197-203 [doi]
• Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor DecompositionZhewen Yu, Christos-Savvas Bouganis. 204-211 [doi]
• GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and OptimizationStefan Abi-Karam, Cong Hao. 212-218 [doi]
• Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference AccelerationPaul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna. 219-227 [doi]
• Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural NetworksRuiqi Chen, Haoyang Zhang, Shun Li, Enhao Tang, Jun Yu 0010, Kun Wang 0005. 228-234 [doi]
• Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CANShashwat Khandelwal, Shanker Shreejith. 235-241 [doi]
• Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAsZizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang 0001. 242-247 [doi]
• MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning AccelerationZhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk. 248-252 [doi]
• Partitioning Large-Scale, Multi-FPGA Applications for the Data CenterMohammadmahdi Mazraeli, Yu Gao, Paul Chow. 253-258 [doi]
• Remote Identification of Neural Network FPGA Accelerators by Power FingerprintsVincent Meyers, Michael Hefenbrock, Dennis Gnad, Mehdi Baradaran Tahoori. 259-264 [doi]
• A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices?Andrew Boutros, Stephen More, Vaughn Betz. 265-270 [doi]
• FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated LearningHuimin Li 0004, Phillip Rieger, Shaza Zeitouni, Stjepan Picek, Ahmad-Reza Sadeghi. 271-276 [doi]
• eGPU: A 750 MHz Class Soft GPGPU for FPGAMartin Langhammer, George A. Constantinides. 277-282 [doi]
• LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer NetworksYueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu 0010, Kun Wang 0005. 283-287 [doi]
• PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN AccelerationAlexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis. 288-293 [doi]
• Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAsShi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer. 294-298 [doi]
• Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAsVaibhav Kashera, Siddhant Jain, Abhishek Banerjee, Suresh Purini. 299-304 [doi]
• GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph MinorsGuanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson. 305-310 [doi]
• Improving the Reliability of FPGA CRO PUFsHayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders. 311-316 [doi]
• FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled ReceptorsRuiqi Chen, Haoyang Zhang, Jun Yu 0010, Kun Wang 0005. 317-321 [doi]
• DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGAYang Liu, Xiaoming He, Jun Yu, Kun Wang. 322-326 [doi]
• Accelerating LSTM-Based High-Rate Dynamic System ModelsEhsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey, Jason D. Bakos, David Andrews 0001, Miaoqing Huang. 327-332 [doi]
• Stress-Resiliency of AI Implementations on FPGAsJonas Krautter, Paul R. Genssler, Gloria Sepanta, Hussam Amrouch, Mehdi B. Tahoori. 333-338 [doi]
• A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAsChristoph Niemann, Michael Rethfeldt, Dirk Timmermann. 339-344 [doi]
• Exploring FPGA Acceleration for Distributed Serverless ComputingZiyi Yang, Suhaib A. Fahmy. 345-346 [doi]
• Challenges Using FPGA Clusters for Distributed CNN TrainingPhilipp Kreowsky, Justin Knapheide, Benno Stabernack. 347-348 [doi]
• Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAsRubén Macias, Sergio Bernabé, Carlos González. 349-350 [doi]
• Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable DevicesZhenya Zang, Uwe Dolinsky, Pietro Ghiglio, Stefano Cherubin, Mehdi Goli, Shufan Yang. 351-352 [doi]
• A Scalable and Cross-Technology Quantum Control ProcessorXiaorang Guo, Martin Schulz 0001. 353-354 [doi]
• Bayesian Optimization for Efficient Heterogeneous MPSoC Based DNN Accelerator Runtime TuningXuqi Zhu, Cong Gao, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier. 355-356 [doi]
• Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing SystemsVeronia Iskandar, Mohamed A. Abd El ghany, Diana Goehringer. 357-358 [doi]
• Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioMLFelix Jentzsch. 359-360 [doi]
• Towards Coarse-Grained Reconfigurable Approximate Computing with CGRAgenHans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi. 361-362 [doi]
• Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA ClustersJustin Knapheide, Philipp Kreowsky, Benno Stabernack. 363 [doi]
• HashCache: High-Performance State Tracking for Resilient FPGA-Based Packet ProcessingMichael Offel, Andreas Ley, Sven Hager. 364 [doi]
• FABulous Demo: Open Source FPGA on Sky130Myrtle Shah, Jakob Ternes, Dirk Koch. 365 [doi]
• FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous PlatformsYunyi Zhao, Yunjia Xia, Rui Loureiro, Hubin Zhao, Uwe Dolinsky, Shufan Yang. 366 [doi]