Jae Hong Roh, Useok Lee, Yongje Lee, Myung Hoon Sunwoo. Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder. In 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021. pages 19-20, IEEE, 2021. [doi]
@inproceedings{RohLLS21,
title = {Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder},
author = {Jae Hong Roh and Useok Lee and Yongje Lee and Myung Hoon Sunwoo},
year = {2021},
doi = {10.1109/ISOCC53507.2021.9613860},
url = {https://doi.org/10.1109/ISOCC53507.2021.9613860},
researchr = {https://researchr.org/publication/RohLLS21},
cites = {0},
citedby = {0},
pages = {19-20},
booktitle = {18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021},
publisher = {IEEE},
isbn = {978-1-6654-0174-6},
}