Low area pipelined circuits by multi-clock cycle paths and clock scheduling

Bakhtiar Affendi Rosdi, Atsushi Takahashi. Low area pipelined circuits by multi-clock cycle paths and clock scheduling. In Fumiyasu Hirose, editor, Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006. pages 260-265, IEEE, 2006. [doi]

@inproceedings{RosdiT06:1,
  title = {Low area pipelined circuits by multi-clock cycle paths and clock scheduling},
  author = {Bakhtiar Affendi Rosdi and Atsushi Takahashi},
  year = {2006},
  doi = {10.1145/1118299.1118367},
  url = {http://doi.acm.org/10.1145/1118299.1118367},
  researchr = {https://researchr.org/publication/RosdiT06%3A1},
  cites = {0},
  citedby = {0},
  pages = {260-265},
  booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006},
  editor = {Fumiyasu Hirose},
  publisher = {IEEE},
  isbn = {0-7803-9451-8},
}