Automated synthesis and verification of embedded systems: wishful thinking or reality?

Wolfgang Rosenstiel. Automated synthesis and verification of embedded systems: wishful thinking or reality?. In Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009. IEEE, 2009. [doi]

@inproceedings{Rosenstiel09,
  title = {Automated synthesis and verification of embedded systems: wishful thinking or reality?},
  author = {Wolfgang Rosenstiel},
  year = {2009},
  doi = {10.1145/1509633.1509635},
  url = {http://doi.acm.org/10.1145/1509633.1509635},
  researchr = {https://researchr.org/publication/Rosenstiel09},
  cites = {0},
  citedby = {0},
  booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009},
  publisher = {IEEE},
  isbn = {978-1-4244-2748-2},
}