A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier

Sounak Roy, Swapna Banerjee. A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. In 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India. pages 323-329, IEEE Computer Society, 2008. [doi]

Authors

Sounak Roy

This author has not been identified. Look up 'Sounak Roy' in Google

Swapna Banerjee

This author has not been identified. Look up 'Swapna Banerjee' in Google