Layout-level design for testability rules for a CMOS cell library

M. Rullán, F. C. Blom, J. Oliver, C. Ferrer. Layout-level design for testability rules for a CMOS cell library. In Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993. pages 214-218, IEEE Computer Society, 1993. [doi]

@inproceedings{RullanBOF93-0,
  title = {Layout-level design for testability rules for a CMOS cell library},
  author = {M. Rullán and F. C. Blom and J. Oliver and C. Ferrer},
  year = {1993},
  doi = {10.1109/EURDAC.1993.410640},
  url = {http://dx.doi.org/10.1109/EURDAC.1993.410640},
  researchr = {https://researchr.org/publication/RullanBOF93-0},
  cites = {0},
  citedby = {0},
  pages = {214-218},
  booktitle = {Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-4350-1},
}