The following publications are possibly variants of this publication:
- A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMsJi-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong June Park. tcas, 63-II(2):141-145, 2016. [doi]
- A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correctionDong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung. esscirc 2012: 181-184 [doi]