Improved wafer-level spatial analysis for I_DDQ limit setting

Sagar S. Sabade, D. M. H. Walker. Improved wafer-level spatial analysis for I_DDQ limit setting. In Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001. pages 82-91, IEEE Computer Society, 2001.

Authors

Sagar S. Sabade

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D. M. H. Walker

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