FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers

Mona Safar, M. Watheq El-Kharashi, Ashraf Salem. FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. In Dominique Borrione, Wolfgang J. Paul, editors, Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings. Volume 3725 of Lecture Notes in Computer Science, pages 384-387, Springer, 2005. [doi]

@inproceedings{SafarES05,
  title = {FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers},
  author = {Mona Safar and M. Watheq El-Kharashi and Ashraf Salem},
  year = {2005},
  doi = {10.1007/11560548_37},
  url = {http://dx.doi.org/10.1007/11560548_37},
  tags = {rule-based, analysis},
  researchr = {https://researchr.org/publication/SafarES05},
  cites = {0},
  citedby = {0},
  pages = {384-387},
  booktitle = {Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings},
  editor = {Dominique Borrione and Wolfgang J. Paul},
  volume = {3725},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {3-540-29105-9},
}