Abstract is missing.
- Is Formal Verification Bound to Remain a Junior Partner of Simulation?Wolfram Büttner. 1 [doi]
- Verification Challenges in Configurable Processor Design with ASIP MeisterMasaharu Imai, Akira Kitajima. 2 [doi]
- Towards the Pervasive Verification of Automotive SystemsThomas In der Rieden, Dirk Leinenbach, Wolfgang J. Paul. 3-4 [doi]
- Wired: Wire-Aware Circuit DesignEmil Axelsson, Koen Claessen, Mary Sheeran. 5-19 [doi]
- Formalization of the DE2 LanguageWarren A. Hunt Jr., Erik Reeber. 20-34 [doi]
- Finding and Fixing FaultsStefan Staber, Barbara Jobstmann, Roderick Bloem. 35-49 [doi]
- Verifying Quantitative Properties Using Bound FunctionsArindam Chakrabarti, Krishnendu Chatterjee, Thomas A. Henzinger, Orna Kupferman, Rupak Majumdar. 50-64 [doi]
- How Thorough Is Thorough Enough?Arie Gurfinkel, Marsha Chechik. 65-80 [doi]
- Interleaved Invariant Checking with Dynamic AbstractionLiang Zhang, Mukul R. Prasad, Michael S. Hsiao. 81-96 [doi]
- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional UnitsMiroslav N. Velev. 97-113 [doi]
- Efficient Symbolic Simulation via Dynamic Scheduling, Don t Caring, and Case SplittingViresh Paruthi, Christian Jacobi 0002, Kai Weber. 114-128 [doi]
- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous ComputationOrna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster. 129-145 [doi]
- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive PartitioningGianfranco Ciardo, Andy Jinqing Yu. 146-161 [doi]
- Real-Time Model Checking Is Really SimpleLeslie Lamport. 162-175 [doi]
- Temporal Modalities for Concisely Capturing Timing DiagramsHana Chockler, Kathi Fisler. 176-190 [doi]
- Regular VacuityDoron Bustan, Alon Flaisher, Orna Grumberg, Orna Kupferman, Moshe Y. Vardi. 191-206 [doi]
- Automatic Generation of Hints for Symbolic TraversalDavid Ward, Fabio Somenzi. 207-221 [doi]
- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization StrategiesJason Baumgartner, Hari Mony. 222-237 [doi]
- A New SAT-Based Algorithm for Symbolic Trajectory EvaluationJan-Willem Roorda, Koen Claessen. 238-253 [doi]
- An Analysis of SAT-Based Model Checking Techniques in an Industrial EnvironmentNina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan. 254-268 [doi]
- Exploiting Constraints in Transformation-Based VerificationHari Mony, Jason Baumgartner, Adnan Aziz. 269-284 [doi]
- Identification and Counter Abstraction for Full Virtual SymmetryOu Wei, Arie Gurfinkel, Marsha Chechik. 285-300 [doi]
- On the Verification of Memory Management MechanismsIakov Dalinger, Mark A. Hillebrand, Wolfgang J. Paul. 301-316 [doi]
- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence VerificationSudhindra Pandav, Konrad Slind, Ganesh Gopalakrishnan. 317-331 [doi]
- Symbolic Partial Order Reduction for Rule Based Transition SystemsRitwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan. 332-335 [doi]
- Verifying Timing Behavior by Abstract Interpretation of Executable CodeChristian Ferdinand, Reinhold Heckmann. 336-339 [doi]
- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and DatapathsMasahiro Fujita. 340-344 [doi]
- Deadlock Prevention in the Æthereal ProtocolBiniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu. 345-348 [doi]
- Acceleration of SAT-Based Iterative Property CheckingDaniel Große, Rolf Drechsler. 349-353 [doi]
- Error Detection Using BMC in a Parallel EnvironmentSubramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle. 354-358 [doi]
- Formal Verification of SynchronizersTsachy Kapschitz, Ran Ginosar. 359-362 [doi]
- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification ProblemsPanagiotis Manolios, Sudarshan K. Srinivasan. 363-366 [doi]
- Improvements to the Implementation of Interpolant-Based Model CheckingJoão P. Marques Silva. 367-370 [doi]
- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware DesignPetr Matousek, Ales Smrcka, Tomás Vojnar. 371-375 [doi]
- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral LogicKatell Morin-Allory, David Cachera. 376-379 [doi]
- Resolving Quartz OverloadingOliver Pell, Wayne Luk. 380-383 [doi]
- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT SolversMona Safar, M. Watheq El-Kharashi, Ashraf Salem. 384-387 [doi]
- Predictive Reachability Using a Sample-Based ApproachDebashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson. 388-392 [doi]
- Minimizing Counterexample of ACTL PropertyShengYu Shen, Ying Qin, Sikun Li. 393-397 [doi]
- Data Refinement for Synchronous System Specification and ConstructionAlex Tsow, Steven D. Johnson. 398-401 [doi]
- Introducing Abstractions via RewritingWilliam D. Young. 402-405 [doi]
- A Case Study: Formal Verification of Processor Critical PropertiesEmmanuel Zarpas. 406-409 [doi]