Miroslav N. Velev. Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. In Dominique Borrione, Wolfgang J. Paul, editors, Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings. Volume 3725 of Lecture Notes in Computer Science, pages 97-113, Springer, 2005. [doi]
Abstract is missing.