Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat. Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. In International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011. pages 67-71, IEEE, 2011. [doi]

This author has not been identified. Look up 'Prabir Saha' in GoogleThis author has not been identified. Look up 'Arindam Banerjee' in GoogleThis author has not been identified. Look up 'Partha Bhattacharyya' in GoogleThis author has not been identified. Look up 'Anup Dandapat' in Google

runs on WebDSL