Table of Contents

• Concurrent Dual Band Transmitter for 2.4/5.2GHz Wireless LAN ApplicationsZubair Akhter, Nagendra P. Pathak. 1-5 [doi]
• Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLLOleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra. 6-11 [doi]
• Performance Study of Harmony Search Algorithm for Analog Circuit SizingShravan Kudikala, Samrat L. Sabat, Siba K. Udgata. 12-17 [doi]
• A Harmonically Superior Switching Modulator with Wide Baseband and Real-Time TunabilityHirak Patangia, Sri Nikhil Gupta Gourisetti. 18-23 [doi]
• A Multiple-Bandwidth 10-bit SAR Analog to Digital ConverterMahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 24-29 [doi]
• Nonlinear Inductance Measurement Using an Energy Storage ApproachManoj Kumar Meena, Rohit Khanna, Dipankar. 30-33 [doi]
• Highly Sensitive ?R/R Measurement System for Nano-electro-Mechanical Cantilever Based Bio-sensorsSandeep Goud Surya, Sudip Nag, Avil J. Fernandes, Sahir Gandhi, Dilip Agarwal, Gaurav Chatterjee, V. Ramgopal Rao. 34-38 [doi]
• PVT-tolerant 7-Transistor SRAM Optimization via Polynomial RegressionSaraju P. Mohanty, Elias Kougianos. 39-44 [doi]
• A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector SupportAlok Baluni, Farhad Merchant, S. K. Nandy, S. Balakrishnan. 45-50 [doi]
• A New Look-Up Table Approach for High-Speed Finite Field MultiplicationBimal Kumar Meher, Pramod Kumar Meher. 51-55 [doi]
• VLSI Implementation of Wavelet Based Robust Image Watermarking ChipT. C. Lad, Anand D. Darji, S. N. Merchant, Arun N. Chandorkar. 56-61 [doi]
• Design of Low Power, High Performance FIR Filter Using Modified Differential Evolution AlgorithmK. Srinivasa Reddy, M. S. Bharath, S. K. Sahoo, S. Sinha, J. P. Reddy. 62-66 [doi]
• Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI ApplicationsPrabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat. 67-71 [doi]
• An Efficient Method for Using Transaction Level Assertions in a Class Based Verification EnvironmentNaveen Sudhish, Raghavendra BR, Harish Yagain. 72-76 [doi]
• Low Complexity Flexible Hardware Efficient Decimation SelectorV. Rakesh, Kavallur Gopi Smitha, A. Prasad Vinod. 77-81 [doi]
• Process Variation Tolerant SRAM Cell DesignSuresh Kumar Varanasi, Satyam Mandavilli. 82-87 [doi]
• Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC SystemsManish M. Patil, Shaila Subbaraman, Shirish Joshi. 88-93 [doi]
• A Method to Reuse RTL Verification Tests to Validate Cycle Accurate ModelManish Baphna, Anchal Jain, Ashish Mathur. 94-99 [doi]
• A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision BlockChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 100-105 [doi]
• Towards Quick Solutions for Generalized Placement ProblemS. Srinivasan 0001, V. Kamakoti, A. Bhattacharya. 106-111 [doi]
• Single-Event Transient Analysis in High Speed CircuitsMohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan. 112-117 [doi]
• A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design TechniqueManisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor. 118-123 [doi]
• A Novel 14-Transistors Low-Power High-Speed PPM AdderRamracksha Tripathi, Shivshankar Mishra, S. G. Prakash. 124-128 [doi]
• Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault CoverageAshok Kumar Suhag, Vivek Shrivastava. 129-133 [doi]
• An Authenticated Encryption Based Security Framework for NoC ArchitecturesK. Sajeesh, Hemangee K. Kapoor. 134-139 [doi]
• Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile ApplicationsRamkumar Jayaraman, Handi Kartadihardja, Douglas L. Maskell. 140-145 [doi]
• Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable ApplicationNachiketa Das, Pranab Roy, Hafizur Rahaman. 146-151 [doi]
• An Improved BitMask Based Code Compression Algorithm for Embedded SystemsWei Jhih Wang, Chang Hong Lin. 152-157 [doi]
• Addressing the Interoperability Issues While Using JPEG-XRHarish Yagain, Srinivas Donapati. 158-163 [doi]
• Automatic Construction of Runtime Monitors for FPGA Based DesignsPratibha Sawhney, G. Ganesh, A. K. Bhattacharjee. 164-169 [doi]
• System on Chip Implementation of Adaptive Moving Average Based Multiple-Model Kalman Filter for Denoising Fiber Optic Gyroscope SignalKarthik K. P., P. Rangababu, Samrat L. Sabat, Jagannath Nayak. 170-175 [doi]
• A Best Path Selection Based Parallel Router for DMFBsPranab Roy, Hafizur Rahaman, Rupam Bhattacharya, Parthasarathi Dasgupta. 176-181 [doi]
• Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon InterconnectsDebaprasad Das, Hafizur Rahaman. 182-187 [doi]
• Optimization of Test Wrapper for TSV Based 3D SOCsSurajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman. 188-193 [doi]
• Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic CircuitsLuo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty. 194-199 [doi]
• Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible CircuitsDipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 200-205 [doi]
• Antenna Considerations for Retail Beamed Power Delivery in IndiaNarayanan M. Komerath, Aravinda Kar, Rajkumar Pant. 206-211 [doi]
• A New BSQDD Approach for Synthesis of Quantum CircuitAmrita Som, Amlan Chakrabarti. 212-216 [doi]
• Threshold Read Method for Multi-bit Memristive Crossbar MemoryYalcin Yilmaz, Pinaki Mazumder. 217-222 [doi]
• Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic BiochipIndrajit Pan, Parthasarathi Dasgupta, Hafizur Rahaman, Tuhina Samanta. 223-229 [doi]
• Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCsSurajit Kumar Roy, Chandan Giri, Arnab Chakraborty, Subhro Mukherjee, Debesh K. Das, Hafizur Rahaman. 230-235 [doi]
• Synthesis of Reversible Universal Logic around QCA with Online TestabilityBibhash Sen, Divyam Saran, Mousumi Saha, Biplab K. Sikdar. 236-241 [doi]
• Application of Lighter-Than-Air Platforms for Power Beaming, Generation and CommunicationsRajkumar Pant, Narayanan M. Komerath, Aravinda Kar. 242-247 [doi]
• Energy Efficient Memory Authentication Mechanism in Embedded SystemsSatyajeet Nimgaonkar, Mahadevan Gomathisankaran. 248-253 [doi]
• Low Active Power High Speed Cache DesignAminul Islam, Mohd. Ajmal Kafeel, Ale Imran, Mohd. Hasan. 254-259 [doi]
• Design and Implementation of Low Power Smart PV Energy System for Portable Applications Using Synchronous Buck ConverterB. Chitti Babu, Sriharsha, M. V. Ashwin Kumar, Nikhil Saroagi, S. R. Samantaray. 260-266 [doi]
• Adiabatic 5T SRAMMamatha Samson, Satyam Mandavalli. 267-272 [doi]
• POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile WorkloadsPriyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul. 273-278 [doi]
• Versatile Battery Chargers for New Age BatteriesHimesh Joshi, Maryam Shojaei Baghini. 279-284 [doi]
• Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled TechnologyS. D. Pable, Mohd. Hasan, Mohd Ajmal Kafeel. 285-289 [doi]
• DCSFPSS Assisted Morphological Approach for Grey Twill Fabric Defect Detection and Defect Area Measurement for Fabric GradingJayashree Vaddin, Shaila Subbaraman. 290-295 [doi]
• MAC Protocol for Two Level QoS Support in Cognitive Radio NetworkVishram Mishra, Chiew Tong Lau, Syin Chan, Jimson Mathew. 296-301 [doi]
• A Novel Variable Mask Median Filter for Removal of Random Valued Impulses in Digital Images (VMM)J. K. Mandal, Somnath Mukhopadhyay. 302-306 [doi]
• Instruction Scheduling on Variable Latency Functional Units of VLIW ProcessorsNayan V. Mujadiya. 307-312 [doi]
• A Message Embedded Authentication of Songs to Verify Intellectual Property Right (MEAS)Uttam Kr. Mondal, J. K. Mandal. 313-317 [doi]
• Low-Cost Software-Implemented Error Detection TechniqueMohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi. 318-323 [doi]
• Image Authentication Using Hough Transform Generated Self Signature in DCT Based Frequency Domain (IAHTSSDCT)Madhumita Sengupta, J. K. Mandal. 324-328 [doi]
• A Novel Technique for Secret Communication through Optimal Shares Using Visual Cryptography (SCOSVC)J. K. Mandal, Subhankar Ghatak. 329-334 [doi]
• A Low-Complexity Speaker-and-Word Recognition Application for Resource-Constrained DevicesGeorge Rosario Dhinesh, George Rosario Jagadeesh, Thambipillai Srikanthan. 335-340 [doi]
• A Novel Fuzzy-GIS Model Based on Delaunay Triangulation to Forecast Facility Locations (FGISFFL)Parthajit Roy, J. K. Mandal. 341-346 [doi]
• A Data-Hiding Scheme for Digital Image Using Pixel Value Differencing (DHPVD)J. K. Mandal, A. Khamrui. 347-351 [doi]
• High Capacity Reversible Data Hiding Using IWTToshanlal Meenpal, Anup K. Bhattacharjee. 352-357 [doi]