Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications - researchr publication

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Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat. Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. In International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011. pages 67-71, IEEE, 2011. [doi]

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