Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop. Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(11):2485-2496, 2018. [doi]
@article{SahooSSMRR18,
title = {Formal Modeling and Verification of Controllers for a Family of DRAM Caches},
author = {Debiprasanna Sahoo and Swaraj Sha and Manoranjan Satpathy and Madhu Mutyam and S. Ramesh and Partha S. Roop},
year = {2018},
doi = {10.1109/TCAD.2018.2857318},
url = {https://doi.org/10.1109/TCAD.2018.2857318},
researchr = {https://researchr.org/publication/SahooSSMRR18},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {37},
number = {11},
pages = {2485-2496},
}