Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique - researchr publication authors

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Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano. Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. In Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha, editors, 2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. pages 329-332, IEEE, 2008. [doi]

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