Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani. An FPGA NIC Based Hardware Caching for Blockchain. In Diana Göhringer, Michael Hübner, editors, Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, June 7-9, 2017. ACM, 2017. [doi]
@inproceedings{SakakibaraNM17,
title = {An FPGA NIC Based Hardware Caching for Blockchain},
author = {Yuma Sakakibara and Kohei Nakamura and Hiroki Matsutani},
year = {2017},
doi = {10.1145/3120895.3120897},
url = {http://doi.acm.org/10.1145/3120895.3120897},
researchr = {https://researchr.org/publication/SakakibaraNM17},
cites = {0},
citedby = {0},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, June 7-9, 2017},
editor = {Diana Göhringer and Michael Hübner},
publisher = {ACM},
isbn = {978-1-4503-5316-8},
}