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2 bit density with 3.2Gbps interface and 205MB/s program throughput

Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, Masaki Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, Kosuke Yanagidaira, Tetsuaki Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, Hiroshi Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe. 2 bit density with 3.2Gbps interface and 205MB/s program throughput. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

Authors

Mario Sako

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T. Nakajima

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Fumihiro Kono

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T. Nakano

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Masaki Fujiu

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Junji Musha

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Dai Nakamura

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Naoaki Kanagawa

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Y. Shimizu

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Kosuke Yanagidaira

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Tetsuaki Utsumi

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T. Kawano

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Yoshikazu Hosomura

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Hiroki Yabe

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M. Kano

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Hiroshi Sugawara

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A. H. Sravan

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K. Hayashi

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Toshiyuki Kouchi

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Y. Watanabe

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