Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, Masaki Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, Kosuke Yanagidaira, Tetsuaki Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, Hiroshi Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe. 2 bit density with 3.2Gbps interface and 205MB/s program throughput. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
@inproceedings{SakoNKNFMNKSYUK23,
title = {2 bit density with 3.2Gbps interface and 205MB/s program throughput},
author = {Mario Sako and T. Nakajima and Fumihiro Kono and T. Nakano and Masaki Fujiu and Junji Musha and Dai Nakamura and Naoaki Kanagawa and Y. Shimizu and Kosuke Yanagidaira and Tetsuaki Utsumi and T. Kawano and Yoshikazu Hosomura and Hiroki Yabe and M. Kano and Hiroshi Sugawara and A. H. Sravan and K. Hayashi and Toshiyuki Kouchi and Y. Watanabe},
year = {2023},
doi = {10.23919/VLSITechnologyandCir57934.2023.10185237},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185237},
researchr = {https://researchr.org/publication/SakoNKNFMNKSYUK23},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
publisher = {IEEE},
isbn = {978-4-86348-806-9},
}