Loop Scheduling for Transport Triggered Architecture Processors

Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala. Loop Scheduling for Transport Triggered Architecture Processors. In International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006. pages 1-4, IEEE, 2006. [doi]

@inproceedings{SalmelaMJT06,
  title = {Loop Scheduling for Transport Triggered Architecture Processors},
  author = {Perttu Salmela and Risto Mäkinen and Pekka Jääskeläinen and Jarmo Takala},
  year = {2006},
  doi = {10.1109/ISSOC.2006.322011},
  url = {https://doi.org/10.1109/ISSOC.2006.322011},
  researchr = {https://researchr.org/publication/SalmelaMJT06},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006},
  publisher = {IEEE},
  isbn = {1-4244-0622-6},
}