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Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto. Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth. IEEE Trans. Parallel Distrib. Syst., 25(3):695-705, 2014. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-BandwidthKentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto. fccm 2011: 234-241 [doi] HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA AcceleratorDaiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano. iccel 2024: 1-6 [doi]
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