Sachin S. Sapatnekar, Weitong Chuang. Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst., 5(1):98-114, 2000. [doi]
@article{SapatnekarC00,
title = {Power-delay optimizations in gate sizing},
author = {Sachin S. Sapatnekar and Weitong Chuang},
year = {2000},
doi = {10.1145/329458.329473},
url = {http://doi.acm.org/10.1145/329458.329473},
tags = {optimization},
researchr = {https://researchr.org/publication/SapatnekarC00},
cites = {0},
citedby = {0},
journal = {ACM Trans. Design Autom. Electr. Syst.},
volume = {5},
number = {1},
pages = {98-114},
}