Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)

Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis. Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). IEEE Transactions on Computers, 64(1):280-285, 2015. [doi]

Authors

Fareena Saqib

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Aindrik Dutta

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Jim Plusquellic

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Philip Ortiz

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Marios S. Pattichis

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