Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis. Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). IEEE Transactions on Computers, 64(1):280-285, 2015. [doi]
@article{SaqibDPOP15,
title = {Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)},
author = {Fareena Saqib and Aindrik Dutta and Jim Plusquellic and Philip Ortiz and Marios S. Pattichis},
year = {2015},
doi = {10.1109/TC.2013.204},
url = {http://doi.ieeecomputersociety.org/10.1109/TC.2013.204},
researchr = {https://researchr.org/publication/SaqibDPOP15},
cites = {0},
citedby = {0},
journal = {IEEE Transactions on Computers},
volume = {64},
number = {1},
pages = {280-285},
}