Dipankar Sarkar. Status Condition Analysis during Data Path Verification of Sequential Circuits. In 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. pages 70-75, IEEE Computer Society, 2000. [doi]
@inproceedings{Sarkar00:2, title = {Status Condition Analysis during Data Path Verification of Sequential Circuits}, author = {Dipankar Sarkar}, year = {2000}, doi = {10.1109/ICVD.2000.812587}, url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812587}, tags = {analysis, data-flow analysis}, researchr = {https://researchr.org/publication/Sarkar00%3A2}, cites = {0}, citedby = {0}, pages = {70-75}, booktitle = {13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India}, publisher = {IEEE Computer Society}, }