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Dipankar Sarkar. Status Condition Analysis during Data Path Verification of Sequential Circuits. In 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. pages 70-75, IEEE Computer Society, 2000. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Register Transfer Operation Analysis during Data Path VerificationD. Sarkar. vlsid 2002: 172 [doi] Register Sharing Verification During Data-Path SynthesisChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade. iccta 2007: 135-140 [doi]
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