An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

Santanu Sarkar 0002, Swapna Banerjee. An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA. pages 268-273, IEEE Computer Society, 2009. [doi]

@inproceedings{SarkarB09,
  title = {An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC},
  author = {Santanu Sarkar 0002 and Swapna Banerjee},
  year = {2009},
  doi = {10.1109/ISVLSI.2009.12},
  url = {http://dx.doi.org/10.1109/ISVLSI.2009.12},
  researchr = {https://researchr.org/publication/SarkarB09},
  cites = {0},
  citedby = {0},
  pages = {268-273},
  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA},
  publisher = {IEEE Computer Society},
}