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Santanu Sarkar 0002, Swapna Banerjee. An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA. pages 268-273, IEEE Computer Society, 2009. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architectureSantanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee. iscas 2008: 149-152 [doi] A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch EffectSantanu Sarkar 0002, Swapna Banerjee. isvlsi 2015: 172-177 [doi]
The following publications are possibly variants of this publication: