Multi-bit fault tolerant design for resistive memories through dynamic partitioning

Sutapa Sarkar, Mousumi Saha, Biplab K. Sikdar. Multi-bit fault tolerant design for resistive memories through dynamic partitioning. In 2017 IEEE East-West Design & Test Symposium, EWDTS 2017, Novi Sad, Serbia, September 29 - October 2, 2017. pages 1-6, IEEE Computer Society, 2017. [doi]

@inproceedings{SarkarSS17,
  title = {Multi-bit fault tolerant design for resistive memories through dynamic partitioning},
  author = {Sutapa Sarkar and Mousumi Saha and Biplab K. Sikdar},
  year = {2017},
  doi = {10.1109/EWDTS.2017.8110053},
  url = {http://doi.ieeecomputersociety.org/10.1109/EWDTS.2017.8110053},
  researchr = {https://researchr.org/publication/SarkarSS17},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {2017 IEEE East-West Design & Test Symposium, EWDTS 2017, Novi Sad, Serbia, September 29 - October 2, 2017},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-3299-4},
}