John Sartori, Rakesh Kumar. Exploiting Timing Error Resilience in Processor Architecture. ACM Trans. Embedded Comput. Syst., 12(2s):89, 2013. [doi]
@article{SartoriK13,
title = {Exploiting Timing Error Resilience in Processor Architecture},
author = {John Sartori and Rakesh Kumar},
year = {2013},
doi = {10.1145/2465787.2465791},
url = {http://doi.acm.org/10.1145/2465787.2465791},
researchr = {https://researchr.org/publication/SartoriK13},
cites = {0},
citedby = {0},
journal = {ACM Trans. Embedded Comput. Syst.},
volume = {12},
number = {2s},
pages = {89},
}