A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi. A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). In Jörg Henkel, Sri Parameswaran, editors, Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009. pages 251-260, ACM, 2009. [doi]

Abstract

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