Toshinori Sato, Itsujiro Arita. Combining variable latency pipeline with instruction reuse for execution latency reduction. Systems and Computers in Japan, 34(12):11-21, 2003. [doi]
@article{SatoA03,
title = {Combining variable latency pipeline with instruction reuse for execution latency reduction},
author = {Toshinori Sato and Itsujiro Arita},
year = {2003},
doi = {10.1002/scj.10498},
url = {http://dx.doi.org/10.1002/scj.10498},
tags = {reuse},
researchr = {https://researchr.org/publication/SatoA03},
cites = {0},
citedby = {0},
journal = {Systems and Computers in Japan},
volume = {34},
number = {12},
pages = {11-21},
}