A 500-MHz pipelined burst SRAM with improved SER immunity - researchr publication related

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Hirotoshi Sato, Tomohisa Wada, Shigeki Ohbayashi, Kunihiko Kozaru, Yasuyuki Okamoto, Yoshiko Higashide, Tadayuki Shimizu, Yukio Maki, Rui Morimoto, Hisakazu Otoi, Tsuyoshi Koga, Hiroki Honda, Makoto Taniguchi, Yutaka Arita, Toru Shiomi. A 500-MHz pipelined burst SRAM with improved SER immunity. J. Solid-State Circuits, 34(11):1571-1579, 1999. [doi]

The following publications are possibly variants of this publication:

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/OKazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto. jssc, 32(11):1758-1765, 1997. [doi]

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