Süleyman Savas, Endri Bezati, Jörn W. Janneck. Generating hardware and software for RISC-V cores generated with Rocket Chip generator. In Gang Qu 0001, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar, editors, 34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021. pages 89-94, IEEE, 2021. [doi]
@inproceedings{SavasBJ21,
title = {Generating hardware and software for RISC-V cores generated with Rocket Chip generator},
author = {Süleyman Savas and Endri Bezati and Jörn W. Janneck},
year = {2021},
doi = {10.1109/SOCC52499.2021.9739411},
url = {https://doi.org/10.1109/SOCC52499.2021.9739411},
researchr = {https://researchr.org/publication/SavasBJ21},
cites = {0},
citedby = {0},
pages = {89-94},
booktitle = {34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021},
editor = {Gang Qu 0001 and Jinjun Xiong and Danella Zhao and Venki Muthukumar and Md Farhadur Reza and Ramalingam Sridhar},
publisher = {IEEE},
isbn = {978-1-6654-2931-3},
}